Girish Arora

Analog IC designAug 2025 to Dec 2025

Wideband Transimpedance Amplifier in 45 nm CMOS

• 1 V CMOS TIA for photodiode front ends.
• 109 dBΩ transimpedance gain, ~492 MHz bandwidth, ~4.5e-14 A²/Hz input-referred noise, 2.76 mW power.

Tools: Cadence Virtuoso, Spectre.

Analog/mixed-signal IC design2024

Phase-Locked Loop for SerDes Clock Generation in 180 nm CMOS

• Charge-pump PLL for SerDes clocking: phase-frequency detector, charge pump with loop filter, 3-stage ring VCO, and frequency divider.
• 4.44 GHz output at 1.8 V supply with 50% duty cycle, from transient simulation (typical corner, 25 °C).

Undergraduate capstone, team of four. Tools: Cadence Virtuoso, Spectre. GitHub repo →

Memory circuit designSep 2025 to Dec 2025

16×4 SRAM Memory Circuit

• Read access delay 3.348 ps.
• Cut power from 131 µW at 1.2 V to 33 µW at 1.0 V through supply-voltage scaling.

NanofabricationJan 2026 to May 2026

Cleanroom Device Fabrication (ESE 5360)

• 60 hours of hands-on cleanroom work: photolithography, EBL, RIE/DRIE plasma etch, PECVD and sputtered thin films, ALD, wet processing, device release.
• Fabricated MEMS actuators on SOI. Verified the 2.6 µm device layer by reflectometry.
• Patterned PS-b-PMMA by directed self-assembly with 23 nm feature heights.
• Also worked on graphene transistors and CdSe quantum dot synthesis.

Power electronicsSep 2026 to present

Power Device Characterization (ESE 5800)

• Characterized an STPS360AF Schottky diode and an IRLML0040 MOSFET from 0.02 to 4 A with pulsed bench measurements.
• Automated the measurements in Python/PyVISA on Keysight E36441A and 34461A instruments.
• Fit simplified models (V_FWD = 0.330 V, R_ON = 66.5 mΩ, R_DS(on) = 65.1 mΩ) and validated them against vendor SPICE models and datasheet curves.

Semiconductor memoryJan 2026 to May 2026

Robust Compute-in-Memory for Edge Healthcare (ESE 5760)

• Modeled OxRAM and PCM 2T2R crossbar non-idealities (RTN, conductance drift) inside hardware-aware training of a 1D-CNN ECG classifier.
• PCM showed 11% lower energy-delay product (0.0275 µJ per inference).

Edge AI hardware2025

NeuroSense

• Real-time mental health monitor that runs entirely on the device. It combines facial emotion recognition, speech cues, and EEG to detect stress, anxiety, and other emotional states.
• Hardware: STM32N6570-DK with its built-in NPU, an EEG front end with instrumentation amplifier and filtering, a YOLOv8-based emotion model, and a TouchGFX touchscreen UI.
• Global 3rd place, Elektor-STM32 Edge-AI Competition 2025. 423+ entries from 31+ countries. €1,000 prize.

With Kartik Khandelwal and Viren Sharma.

Project page on Elektor Labs → Nominee announcement →

Wearable2025

NeuroBand

• Safety armband for elderly and high-risk users. It detects falls and tracks heart rate and ECG. On a fall it sounds an SOS alarm and sends a Wi-Fi alert to a caregiver app with the ECG recorded just before the event.
• Hardware: ESP32-S3 running an on-device fall classifier on accelerometer and gyroscope data, plus heart-rate and ECG sensors.
• Top 10 of 2,959, Circuit Digest Smart Home and Wearables Project Contest 2025.

With Kartik Khandelwal.

Project page on Circuit Digest →

Digital design / FPGA2024

FPGA Flight Controller for a Quadcopter

• Quadcopter flight controller written in HDL on a Basys-3 (Artix-7) FPGA instead of a microcontroller.
• Modules: PWM decoders for throttle, yaw, pitch, and roll from the RC receiver, an I2C master for the MPU-6050 IMU, a PID controller, and a PWM encoder driving the ESCs.
• My part: interfacing the peripherals with the FPGA, the FPV camera, and the PWM encoder and decoder HDL. All four motors synchronized with the transmitter and receiver.

Team project, Thapar. Tools: Xilinx Vivado. GitHub repo →